Academic base of calculations and signals

Content and key concepts

Check date: 2026-09-12. Sources received before implementation. References below are verified material, not a statement to read all works to which they refer.
Questions and experience chap
Chapter
Questions
Sources
10
How do you decode sign/exponent/fraction? What happens when subnormal/overflow? Why is BF16 not equal to FP16? How do we distinguish FP8 encodings? What does FMA mean? Why does the same arithmetic can be rounded up differently? How does reuse change traffic? Why roofline not benchmark? What objects do VRAM occupy when inference/training?
H01,H02,H03,H04; own counts and algebra
11
What signals are indistinguishable after sampling? How does convolution differ from correllation? How do you clearly ask pedding/stream? What does DFT do? When a spectrical work describes a line convolation? how do you apply 2D kernel? How are cannels added together? How is a hand edge filter different from a lirned kernel?
H05,H06,H07,H08; own alias/DFT proofs and gradient fixtures
Sources
H01. Floating Point and IEEE 754 Compliance for NVIDIA GPUs
Nathan Whitehead, Alex Fit-Florea, NVIDIA White Paper (historical text 2011; updated page 2026).
https://docs.nvidia.com/cuda/floating-point/index.html
The content has been obtained: FP32/64, cond-to-nearest ties-toeven, FMA, order of issuances, differences of compiler/library.
We can't take the historical "CPU doesn't have FMA" to modern CPUs.
In the decimal example x=1.008 there are non-consensual bits: their fixture is used by a binary x=1+2x23, b=-(1+2"-22), exact results2\46. This is a technical primary source, not read separately by the regulatory IEE754-2019.
H02. BFloat16: The secret to high performance on Cloud TPUs
Shibo Wang, Pankaj Kanwar, Google Cloud,2019-08-24.
https://cloud.google.com/blog/products/ai-machine-learning/bfloat16-the-secret-to-high-performance-on-cloud-tpus
A description of 1/8/7 fields and BF16 multiply with FP32 accumulation on the specified TPU was received. Research.google address gave 404; the actual use was made of Cloud URL.
Reservation:
The source describes the flush-to-zero subnormals on those TPUs. Our codec shows the abstract BF16 storage with grandual underflow and does not simulate TPU exection. The equal number exponent bits with FP32 does not mean exactly equal min/max final values due to different distribution with.
H03. FP8 Formats for Deep Learning
Paulius Micikevicius et al.,2022, arXiv:2209.05433v2.
https://arxiv.org/abs/2209.05433
Received
abstact and metadata
E4M3 and E5M2; E5 M2 followed by IEEE-lake special encodings, E4 M3 expands the range differently; the laboratory only implements FP8 E5m2; it does not provide a simple e4/m3 codec with infinity for E4m3FN; the quality of learning of large models from abstract is not repeated.
H04. Matrix Multiplication Background User's Guide
NVIDIA, technical guide,2023-02-01.
https://docs.nvidia.com/deeplearning/performance/dl-performance-matrix-multiplication/index.html
The content portion on MxK, K×N,2MKN operations, arythmetic intensity, tiled reuse, division/tal effects. The answer is cut later into a nugation/footer.
Unread Original Roofline Paper
The specific V100/A100 benchmark number is not used as the current universal limit; the phrase "GEMV always memory-bound" is limited to hardware/trade model; we are comparing the introduced B and peak.
H05. Convolutions for Images
Aston Zhang, Zachary C. Lipton, Mu Li, Alexander J. Smola. Dive into Deep Learning, CUP2023, web1.0.3.
https://d2l.ai/_sources/chapter_convolutional-neural-networks/conv-layer.rst.txt
Got RST: correlation video, fixture19/25/37/43, convolution flip, foeature maps/receptive fields, liearning edge kernel. Do not copy the index clause mixing horizontal with i+1: in i=row,j=column. Hand filter and trained kernel are different states. The results of the training from several frames are not announced by ours.
H06. Padding and Stride
The same authors, D2L.2023.
https://d2l.ai/_sources/chapter_convolutional-neural-networks/padding-and-strides.rst.txt
The formulas output shape and examples have been obtained.
on each side
, so the formula includes 2p. We don't promise the same output for different frames with different padding. Zero pedding does not guarantee the same number of uses of each real pixel.
H07. scipy.signal.convolve
SciPy communication, official reference, received version 1.18.0.
https://docs.scipy.org/doc/scipy/reference/generated/scipy.signal.convolve.html
Full/valid/same definitions, length and direction/FFT caveats have been received. Our sliding-window form with explicit p/stride is not called SciPy same. For line convolution, p=K -1, strid1; DFT supplement to N+K - 1 excludes circular advocacy.
H08. scipy.fft.fft
SciPy communication, official reference, received version 1.18.0.
https://docs.scipy.org/doc/scipy/reference/generated/scipy.fft.fft.html
Received forward DFT sum with negative sign, standards, frequancy-bin ordering.
line O(N2) DFT
, not FFT library. Magnitude for display is divided into N; for convolution theorem, the work is made of abnormal transform values.
Limitations on research
DSP Guide Sampling page was requested, but returned the transport arm; it is not read. Aliasing is released for a specific cosine sequence algebraically. The allegation of restoring the restricted signal band is noted with conditions, without a fictional quote from Shannon source. The kit consists of one academic textbook with two sections, technical documentation and one primary abstract; it's a target base, independent of the chapter.
No hardware digit is measured on the student ' s computer. Presets are conditional model parameters. VRAM includes only clearly listed objects; cache, activities, optimizer states and workspace are not equated with weights.